The present invention relates to a clock driver circuit suitable for use in a semiconductor integrated circuit and a method of lay out or routing clock interconnections, and particularly to a clock driver circuit capable of reducing clock skews and a method of routing clock interconnections.
A clock signal has normally been used in a semiconductor integrated circuit to provide synchronization of internal operations. In such a case, clock driver circuits and clock interconnect lines used to distribute a clock signal generated from a clock signal generator lying within the semiconductor integrated circuit or an externally input clock signal to the entire circuit blocks in the semiconductor integrated circuit are commonly provided within the semiconductor integrated circuit.
In a semiconductor integrated circuit required to provide synchronization based on a clock signal, clock interconnect lines are determined according to physical placement of clock driver circuits to which a clock is distributed. Therefore, the lengths of the clock interconnect lines up to their corresponding circuit blocks are unbalanced and hence variations in a conductive line load might occur. As a result, the difference in delay between each individual clock driver circuits occurs and hence a difference occurs between time intervals required to propagate the clock signal to each individual circuit blocks. This will be called xe2x80x9cclock skewxe2x80x9d. This clock skew might produce a circuit malfunction called xe2x80x9cracingxe2x80x9d. It is thus necessary to reduce the clock skew from the viewpoint of the design of the semiconductor integrated circuit.
As the semiconductor integrated circuit which aims to reduce such a clock skew, there is known one disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 7-183778. In a method of routing or lay out clock interconnect lines, which has been disclosed herein, adjacent interconnect lines are set to a conductive line prohibition regions when the clock interconnect lines are formed after the placement of cells used as circuit blocks. Thereafter, paths for the clock interconnect lines are specified so that the distances over which the clock interconnect lines extend from clock drivers to the respective cells, become identical. After the completion of their conductive line, the capacitances of the clock interconnect lines are simulated and the unbalance between the lengths of the clock interconnect lines is calculated. S-shaped additional interconnect lines are formed to equalize the lengths of the clock interconnect lines in each individual systems each other through the use of the conductive line prohibition regions according to the result of calculation. The conductive line capacitances are rendered uniform under the use of the additional interconnect lines, thereby achieving a reduction in clock skew.
Further, Japanese Patent Application Laid-Open No. Hei 11-3945 discloses a clock-tree designing method capable of reducing skews between a plurality of clock signals different in system from each other in a semiconductor integrated circuit activated in synchronism with the plurality of clock signals. According to such a designing method, the clock signals are transmitted through the use of clock buffer cells each having two input terminals to which the two-system clock signals are respectively inputted, and their corresponding two output terminals. Described specifically, two-system clock trees are formed for two clock signals outputted from output terminals of one clock buffer. Two clock signal wires or interconnect lines are wired or routed substantially in parallel through the clock buffer cells as viewed from clock pads to which the clock signals are inputted. Therefore, the lengths of each individual clock signal interconnect lines become equal so that the skews can be reduced.
However, the clock interconnect line routing or lay out method for the semiconductor integrated circuit, which has been described in Japanese Patent Application Laid-Open No. Hei 7-183778 does not take into consideration the clock skews developed due to ununiformity of conductive line capacitance having allowed for the capacitance between the adjacent interconnect lines, conductive line capacitance developed due to the intersection of lower or upper interconnect lines, etc. Further, a problem arises in that since the layout of the clock interconnect lines is determined once and conductive line is modified again after simulation, working time increases.
Further, the clock interconnect line routing method for the semiconductor integrated circuit, which has been described in Japanese Patent Application Laid-Open No. Hei 11-3945, has the merit that since the clock interconnect lines different in system are respectively routed adjacent to one another in advance, a change in adjacent capacitance is low and the skew developed due to it can be reduced. However, the clock interconnect line routing method does not take into consideration control on clock skews based on ununiformity of conductive line capacitance due to the intersection of interlayer interconnect lines. Therefore, a problem arises in that when the ununiformity of conductive line capacitance due to the intersection of the interlayer interconnect lines is high, the significant modification of interconnect lines is required and hence working time increases.
With the foregoing problems in view, it is therefore an object of the present invention to provide a clock driver circuit and a method of routing clock interconnect lines, which are capable of controlling the lengths of adjacent interconnect lines and ununiformity of conductive line capacitance due to the intersection of interlayer interconnect lines.
A clock driver circuit according to the present invention comprises an input terminal to which a single-phase clock signal is inputted, an initial-stage clock driver circuit electrically connected to the input terminal, for converting the single-phase clock signal to positive-phase and anti-phase clock signals, an intermediate clock driver circuit for relaying the positive-phase and anti-phase clock signals outputted from the initial-stage clock driver circuit, a final-stage clock driver circuit for converting the positive-phase and anti-phase clock signals relayed by the intermediate clock driver circuit to a single-phase clock signal, and a pair of interconnect lines for connecting between the initial-stage clock driver circuit and the final-stage clock driver circuit through the intermediate clock driver circuit and transmitting the positive-phase and anti-phase clock signals. The interconnect lines are placed as adjacent to each other.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.